1. Field of the Invention
The present invention relates to a semiconductor device suitable for use in a semiconductor integrated circuit.
2. Description of the Prior Art
There has hitherto been proposed a semiconductor integrated circuit in which a PNP transistor and an NPN transistor having different conductivity types are constructed in a common semiconductor substrate. A transistor having one conductivity type is constructed in the form of a so-called vertical transistor having a normal vertical arrangement while a transistor having the other conductivity type is constructed in the form of a so-called lateral transistor and hence both the PNP and NPN transistors are formed by the same process for simplification of manufacture. This prior art integrated circuit will now be described with reference to FIG. 1.
In one major surface 1a of a semiconductor substrate 1 there are provided N-type island regions 3a and 3b which are separated from each other by an isolation region 2 of, for example, P-type. A P-type region 4 is selectively diffused in the island region 3a and at the same time a P-type region 5 and an annular P-type region 6 surrounding the former are formed in the other island region 3b with the required space maintained therebetween. Then, on the P-type region 4 in the island region 3a there is selectively diffused an N-type region 7 and also in the other island region 3b there is diffused by the same process an N-type region 9' at a side opposite to the region 5 with the region 6 being interposed therebetween. Thus, a vertical NPN transistor trn is constructed with the P-type region 4 and N-type region 7 in the island region 3a which serve as base and emitter regions, respectively and an N-type portion 8 of the island region 3a which serves as a collector region. Further, in the other island region 3b, the P-type regions 5 and 6 are used as a collector (or emitter) region and an emitter (or collector) region, respectively, while an N-type portion 9 between both regions 5 and 6 is used as a base region and the region 9' is used as a low-resistance region for connecting a base electrode, thus constructing a lateral PNP transistor trp wherein the respective regions are disposed in a lateral direction. References 10e, 10b and 10c designate electrodes for connecting an emitter terminal e, a base terminal b and a collector terminal c, respectively, to the NPN transistor trn, and 10E, 10B and 10C electrodes for connecting an emitter terminal E, a base terminal B and a collector terminal C, respectively, to the PNP transistor trp.
In the case when the transistor trp is fabricated in a lateral manner, the respective regions of both transistors can be formed by the same process and the fabrication is simple. In this connection, when both transistors are respectively formed in a vertical manner, the island region 3b has also provided therein regions (though not shown) corresponding to the regions 4 and 7 in the island region 3a. These regions are respectively used as a P-type collector region and an N-type base region and a P-type emitter region must be formed by, for example, diffusion on this base region through another process. Therefore, at least one additional process step is required. An increase in the number of selective diffusion process steps increase production cost.
However, in the transistor trp formed by lateral construction it is desired to provide a space between the collector and emitter regions 5 and 6 as small as possible in order to increase its current-amplification factor h.sub.FE. To this end, a portion for connecting the base electrode 10B should be located, for example, at a position on the side opposite to the region 5 with the region 6 being interposed therebetween. As a result, the lateral transistor trp has a base spreading resistance which becomes too great.